As CMOS technology pushes deeper into the submicron region, some of the most prominent critical issues are cost, performance, and manufacture worthiness of the lithography tool needed for patterning of device dimensions less than 0.35 .mu.m with tight critical dimension (CD) control. I-line lithography has been reliably used in 0.50 .mu.m and 0.35 .mu.m CMOS production However, current I-line lithography is limited to above 0.30 .mu.m. Deep UV (ultraviolet) lithography has been proposed as the incumbent exposure tool of choice, but it currently suffers from many problems such as high capital cost per exposure tool, immaturity in the development of new DUV resist technology, and the availability of robust tools compatible with a full manufacturing environment. An alternative approach to achieving deep-submicron linewidths is resist ashing. Resist ashing techniques have been reported to produce 0.1-0.2 .mu.m polysilicon gate length MOS devices using conventional g-line lithography. However, it is unclear whether this technique can meet the stringent CD control requirements, across the wafer (e.g., &lt;0.025 .mu.m) and from wafer-to-wafer (e.g., 3Sigma=0.025 .mu.m), needed for 0.25 .mu.m processing.